One of the critical features of an integrated circuit design is its testability, the degree to which the fabricated device can be tested for production defects. No matter how perfectly a design functions in simulation, it becomes an unreliable component if it cannot be tested adequately after fabrication.
Since the internal nodes of an integrated circuit are accessible only through its package pins, The testing strategy should include testing individual elements (modules) of the circuit or logic design. The more complex the design, the more difficult it is to test, and the greater the need is to incorporate schemes into the design to enhance testability.
Application specific integrated circuits (ASICs) are among the most complex of all IC designs. ASICs are formed by combining subcircuits (modules) from a cell library to implement the desired function. During design of the ASIC device, the designer can incorporate logic to allow an external testing device to select and isolate one module at a time for testing. A set of input stimuli, designed to ensure high fault coverage for the module, is then applied. The input stimuli are applied in parallel to all input pins of the module at a predetermined rate and the responses of module outputs are sampled and compared to the expected data. Inputs to modules that are not selected are held at their last forced value by means of bus holder circuitry.
One problem associated with the parallel module testability (PMT) described above is the amount of work required to generate test data specific to the integrated circuit in which the module is being used. A given integrated circuit will have a unique set of signals which must be applied to its input pins for testing a module within the integrated circuit. The number of pins and signals that should be applied thereto will vary between integrated circuits, necessitating a customized set of test data. While the test data could be generated manually, such a task would require many man-hours and would involve a high likelihood of error.
Thus, a need has arisen for a fast and reliable method and apparatus of generating test data for input to an integrated circuit to test one or more modules contained therein.